This application relies for priority upon Korean Patent Application No. 1999-42355, filed on Oct. 1, 1999 and No. 2000-46678, filed on Aug. 11, 2000, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to ferroelectric random access memory devices and, more particularly, to a reference voltage generation circuit for ferroelectric random access memory devices.
2. Background of the Invention
A ferroelectric random access memory (hereafter referred to asxe2x80x9cFRAMxe2x80x9d uses a ferroelectric capacitor as a storage element of each memory cell. Each ferroelectric memory cell stores a logic state based upon electric polarization of its ferroelectric capacitor. A ferroelectric capacitor has dielectric material including ferroelectric material such as PZT(PbZrTiO3; lead-zirconate-titanate) between its two electrode plates. When a voltage is applied to both plates of a ferroelectric capacitor, ferroelectric material is polarized toward an electric field. A switching threshold voltage for changing polarization state of a ferroelectric capacitor is called axe2x80x9ccoercive voltagexe2x80x9d
A ferroelectric capacitor exhibits a hysteresis characteristic, and through which current corresponding to its polarization state flows, If a ferroelectric capacitor is biased with an applied voltage higher than its coercive voltage, the capacitor will change its polarization state according to polarity of the applied voltage. The polarization state is maintained even after power down, which makes the memory cell non-volatile.
Polarization states of ferroelectric capacitor can be changed in less time than about 1 nanosecond, which its faster than the programming time of other non-volatile memories, such as flash EEPROMs (electrically erasable programmable read only memories).
Data stored in a ferroelectric memory cell is read out as follows. A voltage is applied to both electrodes of a ferroelectric memory cell capacitor, and then a variation of charges induced on a bit line coupled to the memory cell is sensed. In order to sense the variation of the induced charges(i.e., voltages), a circuit is needed that generates a reference voltage having a voltage value that is intermediate to voltages corresponding to dataxe2x80x9c1xe2x80x9d and dataxe2x80x9c0xe2x80x9d. Conventionally, the reference voltage is generated by use of a reference cell that includes a ferroelectric capacitor having characteristics similar to that of a memory cell.
A perplexing problem in sensing the polarization state of the ferroelectric capacitor in a single capacitor memory cell is that the electric field/polarization characteristic loop (hysteresis curve) of a ferroelectric capacitor changes over time. The change is due to aging from use, or due to aging from being left in a polarization state for an extended time. Generally, this change in polarization properties with time results in a collapsing of the hysteresis curve. This is a basic materials phenomenon that is due to a non-reversibility in at least a portion of the volume of the ferroelectric material under electric field/polarization cycling. This changing of the ferroelectric material makes it very difficult to use a conventional reference cell strategy to determine the polarization state Of ferroelectric memory cells.
A variety of techniques have been suggested to overcome such problems. One solution is described in U.S. Pat. No. 5,432,731, entitledxe2x80x9cFERROELECTRIC MEMORY CELL AND METHOD OF SENSING AND WRITING THE POLARIZATION STATE THEREOFxe2x80x9d issued to Howard C. Kirsch et al., on Jul. 11, 1995. The Kirsch et al. patent described one capacitor ferroelectric memory cell having a reference cell, as reproduced in FIG. 1 of the present document.
Referring to FIG. 1, a simplified one-capacitor ferroelectric memory cell 10 with an associated reference cell 12 is illustrated. Memory cell 10 includes a single switching transistor 15 and a ferroelectric capacitor 20. Generally, to form an array of memory cells, additional memory cells are provided in a first horizontal row that includes memory cell 10. The first row containing memory cell 10 has a WORD line 22 and a PLATE line 23 associated therewith. Additional horizontal rows (not shown) parallel therewith and each including a WORD line and a plate line are provided. Also, memory cell 10 is arranged in a first vertical column with additional memory cells (not shown) having a common BIT line pair 24, 25 connected to a sense amplifier, or latch, 30. Additional columns, each having common BIT line pairs and sense amplifiers are also provided in the array. BIT line 24 is connected to memory cell 10, and to all other memory cells in the first column while BIT line 25 is connected to reference cell 12.
WORD line 22 is connected to the gate of switching transistor 15, and to the gate of switching transistors in each other memory cell in the first row. PLATE line 23, is connected to one plate of ferroelectric capacitor 20, the other plate of which is connected to the drain of switching transistor 15. PLATE line 23 is similarly connected to other memory cells in the first row. The source of switching transistor 15 is connected to BIT line 24 and the sources of switching transistors in all other memory cells in the first column are connected to BIT line 24.
Reference cell 12 is associated with all of the memory cells in the first column. As such, a single reference cell can be used with any memory cell, which allows the use of a single reference cell with each column. Referring to FIG. 1 of the present document, a reference cell 12 has a voltage dumping structure where a reference voltage is supplied onto a bitline BITC. The reference cell 12 includes a first switching transistor 35, a second switching transistor 37, and a reference capacitor 39. A gate of the first switching transistor 35 is connected to an REF WORD line 40, and a source of which is connected to BITC line 25.
One plate of the reference capacitor 39 is connected to a ground, and the other plate is connected to a drain of the first switching transistor 35 and to a source of the second switching transistor 37. A drain of the second switching transistor 37 is connected to a reference potential REF INIT, and a gate of which is connected to receive a reference initial signal,
Using the voltage dumping structure, a reference voltage of DC level is generated to solve the foregoing problem that occurs upon using a reference cell having a ferroelectric capacitor. However, a memory cell is afflicted with a phenomenon that a hysteresis loop of a ferroelectric capacitor changes with time.
Referring to FIG. 2A, a polarization state of a ferroelectric capacitor changes according to an initially ideal curve (indicated by a solid line). And, the ferroelectric capacitor will change according to a deteriorated or collapsing hysteresis curve (indicated by a dotted line) in a predetermined time.
As can be seen in FIG. 2B, a polarization level of a ferroelectric capacitor storing data xe2x80x9c1xe2x80x9d is reduced from point C to point xe2x80x98Cxe2x80x99. On the other hand, the polarization level of a ferroelectric capacitor storing dataxe2x80x9c0xe2x80x9d is increased from point A to point xe2x80x98Axe2x80x99.
Referring to FIG. 2B, which illustrates changes of voltages induced on a bitline with respect to time as the device ages, there is a difference between a reduction ratio of a bitline voltage corresponding to datexe2x80x9c1xe2x80x9d (curve D1) and that of a bitline voltage corresponding to datexe2x80x9c0xe2x80x9d (curve D0). So an optimal sensing margin cannot be secured in a predetermined time.
More particularly, here, the optimal sensing margin means that a sensing margin MD1 between a bitline voltage corresponding to datexe2x80x9c1xe2x80x9d and a reference voltage VREF and a sensing margin MD2 between a bitline voltage corresponding to dataxe2x80x9c0xe2x80x9d and the reference voltage VREF are greater the or identical to required margin. For example, if the sensing margin MD1 is smaller than a required margin and the sensing margin MD0 is greater than the required margin at a time t1, sensing operation of the data MD1 cannot be carried out.
When a hysteresis curve collapses as shown in FIG. 2A, a reference voltage VREF having an intermediate value of bitline voltages of dataxe2x80x9c0xe2x80x9d and dataxe2x80x9c1xe2x80x9d cannot be generated using the reference circuit shown in FIG. 1. This means that life of an FRAM device becomes short, or its reliability is degraded.
The invention overcomes this problem of the prior art.
The invention provides a method and a circuit for generating a query reference voltage for querying an operation cell of a ferroelectric random access memory device for its data. The querying reference voltage has a value that is adjusted with time, to remain between the actual values of the operation cell, notwithstanding degradation of hysteresis due the age and use of the operation cell.
A circuit according to the invention comprises evaluating means for evaluating performance characteristics of ferroelectric cells of the memory device. It also includes generating means for generating a query reference voltage depending on an output of the evaluating means.
The evaluation is preferably performed by interrogating the cells, in order to obtain respective sample characteristics. The sample characteristics are then preferably polled to determine the performance characteristics.
Optionally and preferably, the invention provides additional dummy cells, distinct from the normal operation cells of the device. The dummy cells are dedicated for the evaluation, and ultimately for the generation of the adjustable reference voltage.
These and other features and advantages of the invention will be more clearly understood from the Detailed Description and the Drawing, in which: